1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit such as SOG (Sea Of Gate), wherein unit cells with basic circuits formed therein are formed in a core area of a semiconductor chip in row and column form.
2. Description of the Related Art
In a conventional semiconductor integrated circuit such as SOG or the like, a high-driven driver is inserted between unit cells to control the time required to transfer a signal between the unit cells when a designer designs circuitry. However, no particular countermeasures were taken against its control on a hardware basis.
With miniaturization of semiconductor devices employed in a recent semiconductor integrated circuit devices, however, the proportion of a pass delay to signal increases from a delay time of a signal transmitted through a conventional semiconductor device, e.g., a transistor element itself to a delay time of a signal, which is developed between unit cells due to interconnections.
Therefore, there has been need to take countermeasures for adjusting the time required to transfer the signal between the unit cells.